CY7C1342

The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting in-dependent, asynchronous access for reads and writes to any location in memory. Application areas of CY7C135 and CY7C1342 include interproces-sor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port of CY7C135 and CY7C1342 has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). The CY7C135 is suited for those systems that do not require on-chip arbitration or are intolerant of wait states. Therefore, the user must be aware that simultaneous access to a location is possible. Semaphores are offered on the CY7C1342 to as-sist in arbitrating between ports. The semaphore logic CY7C135 and CY7C1342 is com-prised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indi-cates that a shared resource is in use. An automatic pow-er-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin (CY7C1342 only).

The CY7C135 and CY7C1342 are available in 52-pin PLCC.