CY7C1345F

The CY7C1345F is a 131,072 x 36 synchronous cache RAMdesigned to interface with high-speed microprocessors withminimum glue logic. Maximum access delay from clock rise is6.5 ns (133-MHz version). A 2-bit on-chip counter captures thefirst address in a burst and increments the address automaticallyfor the rest of the burst access. All synchronous inputsare gated by registers controlled by a positive-edge-triggeredClock Input (CLK). The synchronous inputs include alladdresses, all data inputs, address-pipelining Chip Enable(CE₁), depth-expansion Chip Enables (CE₂ and CE₃), BurstControl inputs (ADSC , ADSP , and ADV ), Write Enables(BW_[A:D],and BWE ), and Global Write (GW). Asynchronousinputs include the Output Enable (OE) and the ZZ pin.

The CY7C1345F allows either interleaved or linear burstsequences, selected by the MODE input pin. A HIGH selectsan interleaved burst sequence, while a LOW selects a linearburst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache ControllerAddress Strobe (ADSC ) inputs.

Addresses and chip enables are registered at rising edge ofclock when either Address Strobe Processor (ADSP ) or Address Strobe Controller (ADSC ) are active. Subsequentburst addresses can be internally generated as controlled bythe Advance pin (ADV ).

The CY7C1345F operates from a +3.3V core power supplywhile all outputs may operate with either a +2.5 or +3.3Vsupply. All inputs and outputs are JEDEC-standardJESD8-5-compatible.