CY7C1351

The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1351 is pin/functionally compatible to ZBT SRAMs IDT71V547, MT55L128L36F, and MCM63Z737.

All synchronous inputs of CY7C1351 pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 11.0 ns (66-MHz device).

Write operations of CY7C1351 are controlled by the four Byte Write Select (BWS_[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an asynchronous Output Enable (OE)of CY7C1351 provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers CY7C1351 are synchronously three-stated during the data portion of a write sequence.