CY7C1353F

• Can support up to 133-MHz bus operations with zerowait states
   - Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™devices
• Internally self-timed output buffer control to eliminatethe need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
   - 6.5 ns (for 133-MHz device)
   - 7.5 ns (for 117-MHz device)
   - 8.0 ns (for 100-MHz device)
   - 11.0 ns (for 66-MHz device)
• Clock Enable (CEN ) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability-linear or interleaved burst order
• Low standby power

The CY7C1353F is a 3.3V, 256K x 18 SynchronousFlow-through Burst SRAM designed specifically to supportunlimited true back-to-back Read/Write operations without theinsertion of wait states. The CY7C1353F is equipped with theadvanced No Bus Latency™ (NoBL™) logic required toenable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramaticallyimproves the throughput of data through the SRAM, especiallyin systems that require frequent Write-Read transitions.

All synchronous inputs of CY7C1353F pass through input registers controlledby the rising edge of the clock. The clock input is qualified bythe Clock Enable (CEN ) signal, which when deassertedsuspends operation and extends the previous clock cycle.Maximum access delay of CY7C1353F from the clock rise is 6.5 ns (133-MHzdevice).

Write operations of CY7C1353F are controlled by the two Byte Write Select(BW _[A:B]) and a Write Enable (WE) input. All writes areconducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE₁, CE₂, CE₃) and anasynchronous Output Enable CY7C1353F(OE) provide for easy bankselection and output three-state control. In order to avoid buscontention, the output drivers are synchronously three-statedduring the data portion of a write sequence.