CY7C1354V25

The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36 and 512K by 18 Synchronous-Pipelined Burst SRAMs, respectivelyspectively. They are designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1354V25/CY7C1356V25 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1354V25/CY7C1356V25 is pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs of CY7C1354V25 and CY7C1356V25 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input of CY7C1354V25 and CY7C1356V25 is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.2 ns (200-MHz device).

Write operations of CY7C1354V25 and CY7C1356V25 are controlled by the Byte Write Selects (BWS_aBWS_d for CY7C1354V25 and BWSaBWSb for CY7C1356V25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃)CY7C1354V25 and CY7C1356V25 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers CY7C1354V25 and CY7C1356V25 are synchronously three-stated during the data portion of a write sequence.