CY7C1356B

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and512K x 18 Synchronous pipelined burst SRAMs with No BusLatency™ (NoBL^TM) logic, respectively. They are designed tosupport unlimited true back-to-back Read/Write operationswith no wait states. The CY7C1354B and CY7C1356B areequipped with the advanced (NoBL) logic required to enableconsecutive Read/Write operations with data being transferredon every clock cycle. This feature dramatically improvesthe throughput of data in systems that require frequentWrite/Read transitions. The CY7C1354B and CY7C1356B arepin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. Theclock input is qualified by the Clock Enable ( CEN) signal,which when deasserted suspends operation and extends theprevious clock cycle.

Write operations are controlled by the Byte Write Selects(BW_aBW_d for CY7C1354B and BW_aBW_b for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted withon-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE ₁, CE₂, CE ₃) and anasynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid buscontention, the output drivers are synchronously three-statedduring the data portion of a write sequence.