CY7C1359A

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelin-ing Chip Enable (CE), depth-expansion Chip Enables (CE₂and CE₂), Burst Control Inputs (ADSC, ADSP, and ADV), WriteEnables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN).

Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable.(OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by  (OE) and MOE respectively, are also asynchronous

Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV).

Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE,CE₂, and CE₂). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK).

Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1-DQ9. WEH controls DQ10-DQ18. WEL and WEH can be active only with BWE being LOW. GW being LOW  causes all bytes to be written.

The CY7C1359C/GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8 MB secondary cache.