CY7C1362V25

The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are 2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipelined cache SRAM, respectively. They are designed to support zero wait state secondary cache with minimal glue logic.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.1 ns (200-MHz device).

The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC™. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Select (BW_a,b,c,d for 1360V25/1364V25 and BW_a,b for 1362V25) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.