CY7C1481V33

• Supports 133 MHz bus operations
• 2M x 36/4M x 18/1M x 72 common IO
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
- 6.5 ns (133 MHz version)
• Provide high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481V33, CY7C1483V33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V33 available in Pb-free and non-Pb-free 209 ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• "ZZ" Sleep Mode option

The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V,2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1481V33/CY7C1483V33/CY7C1487V33 include all addresses, all data inputs, address-pipelining Chip Enable (CE₁), depth-expansion Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW).Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables of CY7C1481V33/CY7C1483V33/CY7C1487V33 are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.