Features: • Fast clock speed: 250, 200, and 167 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast access time: 2.6, 3.0, and 3.4 ns
• Optimal for depth expansion
• Single 3.3V 5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1484V33 and CY7C1485V33).
• 165-ball FBGA will be offered on an opportunity basis.
(Please contact Cypress sales or marketing)Pinout
Specificationslines,
not tested.)
Storage Temperature .................................55°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage on VDD Relative to GND........... 0.3V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[10] ............................... 0.5V to VDDQ + 0.5V
DC Input Voltage[10] ........................... 0.5V to VDDQ + 0.5V
Current into Outputs (LOW)........................................... 20 mA
Static Discharge Voltage............................................. > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current....................................................... > 200 mADescriptionThe Cypress Synchronous Burst SRAM family,CY7C1484V33 and CY7C1485V33 employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1484V33 and CY7C1485V33 SRAMs integrate 2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1484V33 and CY7C1485V33 include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data (DQx) and the data parity (DPx) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b and DPa,b apply to CY7C1485V33. a, b, c, and d each are eight bits wide in the case of DQ and one bit wide in the case of DP.
Addresses and chip enables of CY7C1484V33 and CY7C1485V33 are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls of CY7C1484V33 and CY7C1485V33 are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQ and DPd. BWa, BWb, BWc, BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle.The CY7C1484V33 and CY7C1485V33 also incorporate pipelined enable circuit for easy depth expansion without penalizing system performance.
The CY7C1484V33/CY7C1485V33 are both double-cycle deselect parts.All inputs and outputs of the CY7C1484V33,CY7C1485V33 are JEDEC standard JESD8-5-compatible.
CY7C1484V33-200AC Data Sheet
