CY7C150

The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles.

Separate I/O paths of  CY7C150 eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion.

Reset is initiated by selecting  CY7C150 (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time.

Writing to  CY7C150 is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D₀-D₃) is written into the memory location specified on the address pins (A₀ through A9).

Reading  CY7C150  is accomplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O₀ through O₃).

The output pins of  CY7C150 remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW.

A die coat is used to insure alpha immunity.