CY7C1512V18

The CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array.

The Read port of CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 have dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1510V18) or 9-bit words (CY7C1525V18) or 18-bit words (CY7C1512V18) or 36-bit words (CY7C1514V18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds."

Depth expansion of CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 are accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs of CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.