Purchase CY7C1516AV18, In-stock CY7C1516AV18 From SeekIC.
Part Number: CY7C1516AV18
Description: The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18 and CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM equ
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CY7C1516AV18
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DataSheet
General Description
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CY7C1516AV18 Quality Supplier:
BONASE(HK) ELECTRONICS CO., LIMITED COMPANY
Contact: Mr.Vincent
Tel: 0755-8257-9312
Adddate: 2010-09-03
(1027)
Contact: Ms.Mency
Tel: +86-0755-83014238
Adddate: 2010-09-03
(342)
Contact: Mr.Tony
Tel: +86-755-82862373
Adddate: 2010-09-03
(67)
About CY700SMS
PDF/DataSheet Download
Datasheet: CY700SMS
File Size: 311542 KB
Manufacturer: POWER-ONE [Power-One]
Download : Click here to Download
General Description
The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18 and CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock.Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1516AV18 and two 9-bit words in the case of CY7C1527AV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1516AV18 and CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device.
Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Maximum Ratings
Storage Temperature ....................................................–65°C to + 150°C
Ambient Temperature with Power Applied ....................–10°C to + 85°C
Supply Voltage on VDD Relative to GND......................... –0.5V to + 2.9V
Supply Voltage on VDDQ Relative to GND ..................... –0.5V to + VDD
DC Applied to Outputs in High-Z................................... –0.5V to VDD+ 0.3V
DC Input Voltage[15] ...................................................–0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)......... >2001V
Latch-up Current.......................................................... >200 mA
Ambient Temperature with Power Applied ....................–10°C to + 85°C
Supply Voltage on VDD Relative to GND......................... –0.5V to + 2.9V
Supply Voltage on VDDQ Relative to GND ..................... –0.5V to + VDD
DC Applied to Outputs in High-Z................................... –0.5V to VDD+ 0.3V
DC Input Voltage[15] ...................................................–0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)......... >2001V
Latch-up Current.......................................................... >200 mA
Features
• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• DDR-II operates with 1.5 cycle read latency when DLL is enabled
• Operates like a DDR I device with 1 cycle read latency in DLL off mode
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• DDR-II operates with 1.5 cycle read latency when DLL is enabled
• Operates like a DDR I device with 1 cycle read latency in DLL off mode
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
