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CY7C172A

Features: • Automatic power-down when deselected• CMOS for optimum speed/power• High speed -tAA = 15 ns• Transparent write (7C171A)• Low active power -375 mW• Low standby power -93 mW• TTL-compatible inputs and outputs• Capable of withstanding greate...

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CY7C172A: Features: • Automatic power-down when deselected• CMOS for optimum speed/power• High speed -tAA = 15 ns• Transparent write (7C171A)• Low active power -375 mW• Low...

CY7C172A Data Sheet

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Part Number:
CY7C172A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
   -tAA = 15 ns
• Transparent write (7C171A)
• Low active power
   -375 mW
• Low standby power
   -93 mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electrostatic discharge


Pinout

Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... -65°C to +150°C
Ambient Temperature with
Power Applied.................................................. -55°C to +125°C
Supply Voltage to Ground Potential..................-0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................-0.5V to +7.0V
DC Input Voltage .................................................-3.0V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA


Description

The CY7C171A and CY7C172A are high-performance CMOS static RAMs organized as 4096 by 4 bits with separate I/O. Easy memory expansion is provided by an active LOW chip enable (CE) and three-state drivers. The CY7C171A and CY7C172A have an automatic power-down feature, reducing the power consumption by 77% when deselected.

Writing to CY7C171A and CY7C172A are accomplished when the chip enable (CE) and write enable (WE) inputs are both LOW. Data on the four input/output pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A11). Reading theCY7C171A and CY7C172A are accomplished by taking chip enable (CE) LOW, while write enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins.

The output pins of CY7C171A and CY7C172A  remain in a high-impedance state when write enable (WE) is LOW (7C172A only), or chip enable is HIGH.

A die coat is used to insure alpha immunity.




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