CY7C182

The CY7C182 is a high-speed CMOS static RAM organized as 8,192 by 9 bits and it is manufactured using Cypress's highperformance CMOS technology. Access times as fast as 25 ns are available with maximum power consumption of only 770 mW.

The CY7C182, which is oriented toward cache memory applications, features fully static operation requiring no external clocks or timing strobes. The automatic power-down feature reduces the power consumption by more than 70% when the circuit is deselected. Easy memory expansion is provided by an active-LOW Chip Enable (CE₁), an active HIGH Chip Enable (CE₂), an active-LOW Output Enable (OE), and threestate drivers.

An active-LOW Write Enable signal (WE) controls the writing/ reading operation of the memory. When CE₁ and WE inputs are both LOW, data on the nine data input/output pins (I/O0 through I/O8) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, (CE₁ and OE active LOW and CE₂ active HIGH), while (WE) remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the nine data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.

A die coat is used to insure alpha immunity.