CY7C185-35PC

Series: -
Voltage - Supply: 4.5 V ~ 5.5 V
Packaging: Tube
Operating Temperature: 0°C ~ 70°C
Memory Size: 64K (8K x 8)
Format - Memory: RAM
Interface: Parallel
Memory Type: SRAM - Asynchronous
Speed: 35ns
Supplier Device Package: 28-PDIP
Manufacturer: Cypress Semiconductor Corp
Package / Case: 28-DIP (0.300", 7.62mm)


Features:

• High speed
-15 ns
• Fast tDOE
• Low active power
-715 mW
• Low standby power
-220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected


Pinout




Specifications

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[3] .......................................... 0.5V to +7.0V
DC Input Voltage[3]....................................... 0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA


Description

The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. The CY7C185 has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE) controls the writing/ reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the CY7C185 is accomplished by selecting the CY7C185 and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

The input/output pins of CY7C185 remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.