CY7C185

The CY7C185 is a high-performance CMOS static RAM orga-nized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE</a>₁), an active HIGHchip enable (CE</a>₂), and active LOW output enable (OE</a>) and three-state drivers. This device has an automatic power-down
feature (CE</a>₁ or CE</a>₂), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE</a>) controls the writ-ing/reading operation of the memory. When CE</a>₁ and WE</a> in- puts are both LOW and CE</a>₂ is HIGH, data on the eight data input/output pins (I/O₀ through I/O₇) is written into the memory location addressed by the address present on the address pins (A₀ through A₁₂). Reading the device is accomplished by selecting the device and enabling the outputs, CE</a>₁ and OE</a> active LOW, CE</a>₂ active HIGH, while WE</a> remains inactive or HIGH. Under these conditions, the contents of the location ad- dressed by the information on address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE</a>) is HIGH. A die coat is used to insure alpha immunity.