MFG:CYPRESS Package Cooled:PLCC D/C:05/06+
MFG: CYPRESS
Package Cooled: PLCC
D/C: 05/06+
Description: The CY7C342 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to conf...
The CY7C342 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions.
The 128 macrocells in the CY7C342 are divided into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.
Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342 allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342 reduces board space, part count, and increases system reliability.
CY7C342
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The CY7C341B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within theCY7C341B. The MAX® architecture is 100% user-configurable, allowing the devices to accom- modate a variety of independe...
The CY7C341 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within theCY7C341. The MAX architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic ...
The Cypress Multiple Array Matrix (MAX®)CY7C340 family of EPLDs provides a user-configurable, high-density solution to general- purpose logic integration requirements. With the combination of innovative architecture and state-of-the-art process, the MAX ...
The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very high performance state machines.The architecture of the CY7C335, consisting of the...
The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources of CY7C331include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the ...
The CY7C291A, CY7C292A, and CY7C293A are high-perfor-mance 2K-word by 8-bit CMOS PROMs. The CY7C291A, CY7C292A, and CY7C293Aare functionally identical, but are packaged in 300-mil (7C291A, 7C293A) and 600-mil wide plastic and hermetic DIP packages (7C292A).T...
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