MFG:CYPRESS Package Cooled:DIP D/C:05/06+
MFG: CYPRESS
Package Cooled: DIP
D/C: 05/06+
Description: Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 repre...
Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 represents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 "buried" registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB.
The speed and density of the CY7C344 makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial "glue" logic, without using multiple chips. This architectural flexibility allows the CY7C344 to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.
CY7C344
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The CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages.The CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources of CY7C343B are divided into f...
The CY7C343 is a high-performance, high-density erasableprogrammable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources of CY7C343 are divided into four...
The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the CY7C342B to ccommodate a variety of independent ...
The CY7C342-30JC is one member of the CY7C342 family and CY7C342-30JC is designed as the erasable programmable logic device that has some points of features:(1)128 macrocells in eight logic array blocks (LABs); (2)Eight dedicated inputs, 52 bidirectional I/O...
The CY7C342 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within theCY7C342. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic ...
The CY7C341B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within theCY7C341B. The MAX® architecture is 100% user-configurable, allowing the devices to accom- modate a variety of independe...
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