Features: • High-performance, high-density replacement for TTL, 74HC, and custom logic• 32 macrocells, 64 expander product terms in one LAB• 8 dedicated inputs, 16 I/O pins• 0.8-micron double-metal CMOS EPROM technology (CY7C344)• Advanced 0.65-micron CMOS EPROM techn...
CY7C344B20WMB: Features: • High-performance, high-density replacement for TTL, 74HC, and custom logic• 32 macrocells, 64 expander product terms in one LAB• 8 dedicated inputs, 16 I/O pins• ...
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Available in a 28-pin 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344/CY7C344B represents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins of CY7C344/CY7C344B communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 "buried" registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB.
The speed and density of the CY7C344/CY7C344B makes it a natural for all types of applications. With just the CY7C344/CY7C344B, the designer can implement complex state machines, registered logic, and combinatorial "glue" logic, without using multiple chips. This architectural flexibility allows the CY7C344/CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.