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Description: The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of th...


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CY7C373i General Description


The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C373i is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs.

Like all of the UltraLogic™ FLASH370i devices, the CY7C373i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins.The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.

CY7C373i Maximum Ratings

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ....................................65 to +150
Ambient Temperature with
Power Applied................................................55 to +125
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
DC Program Voltage ......................................................12.5V
Output Current into Outputs.........................................16 mA
Static Discharge Voltage ........................................... >2001V
(per MILSTD883, Method 3015)
Latch-Up Current..................................................... >200 mA

CY7C373i Features

• 64 macrocells in four logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
-JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
-fMAX = 125 MHz
-tPD = 10 ns
-tS = 5.5 ns
-tCO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC and 100-pin TQFP packages
• Pin compatible with the CY7C374i

CY7C373i Connection Diagram

CY7C373i  Connection Diagram

CY7C373i datasheet

CY7C373i
PDF/DataSheet Download

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