CY7C409A

 The CY7C408A and CY7C409A are 64-word deep by 8- or9-bit wide first-in first-out (FIFO) buffer memories. In addition to the industry-standard handshaking signals, almost full/almost empty (AFE) and half-full (HF) flags are provided.

AFE is HIGH when the FIFO CY7C408A and CY7C409A is almost full or almost empty, otherwise AFE is LOW. HF is HIGH when the FIFO is half full, otherwise HF is LOW.

The CY7C408A has an output enable (OE) function. The memory CY7C408A and CY7C409A accepts 8- or 9-bit parallel words as its inputs (DI₀ DI₈) under the control of the shift in (SI) input when the input ready (IR) control signal is HIGH. The data is output, in the same order as it was stored on the DO₀ DO₈ output pins under the control of the shift out (SO) input when the output ready (OR) control signal CY7C408A and CY7C409A is HIGH. If the FIFO is full (IR LOW), pulses at the SI input are ignored; if the FIFO is empty (OR LOW), pulses at the SO input are ignored.

The IR and OR signals of CY7C408A and CY7C409A are also used to connect the FIFOs CY7C408A and CY7C409A in parallel to make a wider word or in series to make a deeper buffer, or both.

Parallel expansion CY7C408A and CY7C409A for wider words is implemented by logically ANDing the IR an OR outputs (respectively) of the individual FIFOs together (Figure 5). The AND operation insures that all of the FIFOs CY7C408A and CY7C409A are either ready to accept more data (IR HIGH) or ready to output data (OR HIGH) and thus compensate for variations in propagation delay times between devices.

Serial expansion CY7C408A and CY7C409A (cascading) for deeper buffer memories is accomplished by connecting data outputs of the FIFO closet to the data source (upstream device) to the data inputs of the following (downstream) FIFO (Figure 4). In addition, to insure proper operation, the SO signal of the upstream FIFO CY7C408A and CY7C409A must be connected to the OR output of the upstream FIFO. In this serial expansion configuration, the IR and OR signals are used to pass data through the FIFOs.

Reading and writing operations are completely asynchronous, allowing the FIFO to be used as a buffer between two digital machines of widely differing operating frequencies. The high shift in and shift out rates of these FIFOs, and their throughput rate due to the fast bubblethrough time, which is due to their dual-port RAM architecture, make them ideal for high-speed communications and controllers.