CY7C4282V

The CY7C4282V/92V are high-speed, low-power, first-in firstout (FIFO) memories with clocked read and write interfaces.

The CY7C4282V/92V  are 9 bits wide. The CY7C4282V/92V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. The CY7C4282V/92V  provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering.

The CY7C4282V/92V  have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a Write Enable pin (WEN).

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on the CY7C4282V/92V.

Depth expansion of the CY7C4282V/92V is possible using the Cascade Input (XI), Cascade Output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. TheFL pin of the first device is tied to V_SS and the FL pin of all the remaining devices should be tied to V_CC When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO of the CY7C4282V/92V on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4282V/92V have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable.