CY7C955

Features: • WAN and LAN ATM physical layer device• Provides complete physical layer transport of ATM cells at: -STS−3c/ STM−1 rate of 155.52 MHz -STS−1 rate of 51.84 MHz• Compliant with ATM Forum User Network Interface 3.1 specification• UTOPIA ATM interfa...

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SeekIC No. : 004320534 Detail

CY7C955: Features: • WAN and LAN ATM physical layer device• Provides complete physical layer transport of ATM cells at: -STS−3c/ STM−1 rate of 155.52 MHz -STS−1 rate of 51.84 MH...

floor Price/Ceiling Price

Part Number:
CY7C955
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

• WAN and LAN ATM physical layer device
• Provides complete physical layer transport of ATM cells at:
  -STS−3c/ STM−1 rate of 155.52 MHz
  -STS−1 rate of 51.84 MHz
• Compliant with ATM Forum User Network Interface 3.1 specification
• UTOPIA ATM interface
• ATM cell processing including:
  -HEC generation/verification
  -Cell scrambling/descrambling
  -Rate adaption/idle cell filtering
  -Local Flow Control
  -Cell alignment
• SONET frame processing including:
  -Compliant with Bellcore GR−253, I.432, T1.105, and G.709 for Jitter Tolerance and Jitter Generation
  -Frame generation/recovery
  -SONET scrambling/descrambling
  -Frequency justification/pointer processing
• Complete line interface including:
  -Clock and data recovery
  -Transmit timing derived from receiver or byte-rate source
  -SONET compliant PLL
  -100K PECL compatible I/O
• Alarm indications including:
  -Loss Of Signal
  -Out Of Frame, Loss Of Frame
  -Line Far End Receive Failure
  -Line Alarm Indication Signal
  -B1 Parity Error
  -Loss Of Cell Alignment
  -Loss Of Receive Data
• Controller interface for internal interrupt and configuration registers including:
  -Error monitoring
  -Status indication
  -Device configuration
• 0.65µ Low Power CMOS
• 128-pin PQFP



Pinout

  Connection Diagram


Specifications

Storage Temperature ................................ 40°C to +125°C
Ambient Temperature under Bias ................ −40°C to +85°C
Supply Voltage to Ground Potential ............... 0.5V to +6.0V
DC Input Voltage............................................ 0.5V to +7.0V
DC Input Current ........................................................±20 mA
Static Discharge Voltage ...........................................± 2000V
(per MIL-STD-883, Method 3015)
Latch-Up Current.......................................................±100 mA
Lead Temperature ........................................................300°C
Maximum Junction Temperature ..................................155°C
Maximum Power Dissipation ........................................ 1.5 W




Description

The Cypress Semiconductor CY7C955 is a Transceiver chip designed to carry ATM cells across SONET/SDH systems.

On the transmit side of the CY7C955 , ATM cells coming from the Utopia interface are being mapped into SONET/SDH frames and then serialized for transmission over fiber or twisted pair (through an optical module or an equalizer chip).

On the receive side of the CY7C955, serial SONET/SDH datastreams coming from an optical module or an equalizer chip are being recovered by the intergrated clock and data recovery phase-locked loop, framed, processed, and presented as parallel ATM cells on the Receive Utopia Interface.

The CY7C955 can be used in a Network Interface Card (NIC) design to connect the segmentation and Reassembly (SAR) chip to the optical modules or equalizer chip.

The CY7C955 can also be used in work group or enterprise switches to connect the I/O FIFOs of the switch fabric to the optical module or equalizer in the interface boards.

The applications of the CY7C955 include adapters, switches, routers, hubs, and proprietary systems.




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