DP83256-AP

Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 125 MHz reference
Alternate PMD Interface (DP83256-AP57) supports UTP twisted pair FDDI PMDs with no external clock recovery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNEPC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control Bus Interface
Two levels of on-chip loopback
4B/5B encoderdecoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detectorgenerator
Supports single attach stations dual attach stations
and concentrators with no external logic
DP83256 for SASDAS single path stations
DP83257 for SASDAS singledual path stations
DP83256-AP for SASDAS single path stations that require the alternate PMD interface