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Description: The DP83850C 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC, is designed specifically to meet ...


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DP83850C General Description


The DP83850C 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC, is designed specifically to meet the needs of today's high speed Ethernet networking systems. The DP83850C is fully compatible with the IEEE 802.3 repeater's clause 27.

The DP83850C supports up to twelve 100 Mb/s links with its network interface ports. The 100RIC can be configured to be used with either 100BASE-TX or 100BASE-T4 PHY technologies. Larger repeaters with up to 372 ports may be constructed by cascading DP83850Cs together using the built-in Inter Repeater bus.

In conjunction with a DP83856 100 Mb/s Repeater Information Base device, a DP83850C based repeater becomes a managed entity that is compatible with IEEE 802.3u (clause 30), collecting and providing an easy interface to all the required network statistics.

DP83850C Maximum Ratings

Supply Voltage (Vdd)                            -0.5 V to 7.0V
Supply voltage (Vdd)                              5 volts + 5%
DC Input Voltage (Vin)               -0.5 V to Vcc + 0.5 V
Ambient Temperature (Ta)                           0 to 70c
DC Output Voltage (Vout)           -0.5 V to Vcc + 0.5V
Storage Temperature Range (Tstg)        -65c to 150c
Power Dissipation (Pd)                                  1.575 W
Lead Temp (Tl) (soldering 10-sec)                     260c
ESD Rating 2.0KV
(Rzap = 1.5k, Czap = 120pF)

DP83850C Features

· IEEE 802.3u repeater and management compatible
· Supports Class II TX translational repeater and Class I T4 repeater
· Supports 12 network connections (ports)
· Up to 31 repeater chips cascadable for larger hub applications (up to 372 ports)
· Separate jabber and partition state machines for each port
· Management interface to DP83856 allows all repeater MIBs to be maintained
· Large per-port management counters - reduces management CPU overhead
· On-chip elasticity buffer for PHY signal re-timing to the DP83850C clock source
· Serial register interface - reduces cost
· Physical layer device control/status access available via
the serial register interface
· Detects repeater identification errors
· 132 pin PQFP package

DP83850C Typical Application

The DP83850C's interface to DP83840A PHY devices is fully described in the Application Note AN1069 "100BASE-TX Unmanaged Repeater Design Recommendations". Designers should be aware that there are significant issues involved in the signal timing, loading and layout of this interface and they should consult this Application Note and/or their National Semiconductor representative prior to attempting a design. Further system timing analysis shows that the RXD[3:0], RX_DV and RX_ER signals should be latched into the DP83850C from the connected DP83840s. Figure 5 shows the recommended scheme. This ensures system timing can be met for hub stacks.

DP83850C Connection Diagram

DP83850C  Connection Diagram

DP83850C datasheet

DP83850C
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