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Part Number: DP83865BVH
Description: The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T,100BASE-TX...
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DP83865BVH
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DataSheet
General Description
DP83865BVH General Description
The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T,100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductor's South Portland, Maine facility.
The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII) or the IEEE 802.3z Gigabit Media Independent Interface (GMII).
The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mb/s equipment with 10/100/1000 Mb/s networking infrastructure.
DP83865BVH Features
Fully compliant with IEEE 10BASE-T, 100BASE-TX and 1000BASE-T specifications (802.3u, 802.3z, 802.3ab).
Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12.
3.3 V or 2.5 V MAC interfaces:
IEEE 802.3u MII
IEEE 802.3z GMII
User programmable GMII pin ordering.
IEEE 802.3u Auto-Negotiation and Parallel Detection
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
LED support for activity, full / half duplex, link1000, ink100 and link10 or user programmable (manual on/off).
Supports 25 MHz operation with crystal or oscillator.
Requires only two power supplies, 1.8 V (core and ana-og) and 2.5 V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage.
User programmable interrupt.
Supports Auto-MDIX at 10, 100 and 1000 Mb/s.
Supports JTAG (IEEE1149.1).
Ultra low power consumption of one watt typical.
Management port (MDC / MDIO).
128-pin PQFP package (14mm x 20mm).
WOL support.
Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12.
3.3 V or 2.5 V MAC interfaces:
IEEE 802.3u MII
IEEE 802.3z GMII
User programmable GMII pin ordering.
IEEE 802.3u Auto-Negotiation and Parallel Detection
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
LED support for activity, full / half duplex, link1000, ink100 and link10 or user programmable (manual on/off).
Supports 25 MHz operation with crystal or oscillator.
Requires only two power supplies, 1.8 V (core and ana-og) and 2.5 V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage.
User programmable interrupt.
Supports Auto-MDIX at 10, 100 and 1000 Mb/s.
Supports JTAG (IEEE1149.1).
Ultra low power consumption of one watt typical.
Management port (MDC / MDIO).
128-pin PQFP package (14mm x 20mm).
WOL support.
DP83865BVH Typical Application
10/100/1000 Mb/s capable node cards
Switches with 10/100/1000 Mb/s capable ports
High speed uplink ports (backbone)
Switches with 10/100/1000 Mb/s capable ports
High speed uplink ports (backbone)
DP83865BVH
PDF/DataSheet Download
- Datasheet: DP83865BVH
- File Size: 32737 KB
- Manufacturer: NSC [National Semiconductor]
- Click here to Download
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