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Description: The DP83902A Serial Network Interface Controller for Twisted Pair (ST-NIC) is a microCMOS VLSI device ...


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DP83902A General Description


The DP83902A Serial Network Interface Controller for Twisted Pair (ST-NIC) is a microCMOS VLSI device designed for easy implementation of CSMA/CD local area networks. These include Ethernet (10BASE5), Thin Ethernet (10BASE2) and Twisted-pair Ethernet (10BASE-T). The overall ST-NIC solution provides the Media Access Control (MAC) and Encode-Decode (ENDEC) with an AUI interface, and 10BASE-T transceiver functions in accordance with the IEEE 802.3 standards.

The DP83902A's 10BASE-T transceiver fully complies with the IEEE standard. This functional block incorporates the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity blocks as defined in the standard. The transceiver when combined with equalization resistors, transmit/receive filters, and pulse transformers provides a complete physical interface from the DP83902A's ENDEC module and the twisted pair medium.

The integrated ENDEC module allows Manchester encoding and decoding via a differential transceiver and phase lock loop decoder at 10 Mbit/sec. Also included are collision detect translator and diagnostic loopback capability. The ENDEC module interfaces directly to the transceiver module, and also provides a fully IEEE compliant AUI (Attachment Unit Interface) for connection to other media transceivers.

DP83902A Maximum Ratings

Supply Voltage (VCC) b0.5V to a.................................7.0V
DC Input Voltage (VIN) b0.5V to VCC a ......................0.5V
DC Output Voltage (VOUT) b0.5V to VCC a................ 0.5V
Storage Temperature Range (TSTG) b65§C to a......150§C
Power Dissipation (PD) 800 mW
Lead Temp. (TL) (Soldering, 10 sec.) .......................260§C
ESD Rating (RZAP e 1.5k, CZAP e 100 pF) ...............1.5 kV
Pin to Pin
Pin to GND
Pin to VCC (g1 ZAP)
Clamp Diode Current g............................................20 mA
Note: Absolute Maximum ratings are those values beyond
which the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be operated at
these limits.
Note:All specifications in this datasheet are valid only if the
mandatory isolation is employed and all differential signals
are taken to exist at the AUI or TPI side of the isolation.

DP83902A Features

· Single chip solution for IEEE 802.3, 10BASE-T
· Integrated controller, ENDEC, and transceiver
· Full AUI interface
· No external precision components required
· 3 levels of loopback supported
  Transceiver Module
· Integrates transceiver electronics, including:
· Transmitter and receiver
· Collision detect, heartbeat and jabber timer
· Link integrit· test
· Link disable and polarity detection/correction
· Integrated smart receive squelch
· Reduced squelch level for extended distance cable operation
  (100-pin QFP version) ENDEC Module
· 10 Mb/s Manchester encoding/decoding, plus clock recover·
· Transmitter half or full step mode
· Squelch on receive and collision pairs
· Lock time 5 bits typical
· Decodes Manchester data with up to g18 ns jitter
  MAC/Controller Module
· 100% DP8390 software/hardware compatible
· Dual 16-bit DMA channels
· 16-b·te internal FIFO
· Efficient buffer management implementation
· Independent s·stem and network clocks
· Supports physical, multicast and broadcast address filtering
· Network statistics storage

DP83902A Connection Diagram

DP83902A  Connection Diagram

DP83902A datasheet

DP83902A
PDF/DataSheet Download

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