DS21Q42

Features:

  Four T1 DS1/ISDNPRI/J1 framingtransceivers
   All four framers are fully independent
   Each of the four framers contain dual two
   frame elastic store slip buffers that can connectto asynchronous backplanes up to 8.192 MHz
   8bit parallel control port that can be useddirectly on either multiplexed or nonmultiplexed buses (Intel or Motorola)
   Programmable output clocks for Fractional T1
   Fully independent transmit and receivefunctionality
   Integral HDLC controller with 64-byte buffersconfigurable for FDL or DS0 operation
  Generates and detects inband loop codes from1 to 8 bits in length including CSU loop codes
  Pin compatible with DS21Q44 E1 EnhancedQuad E1 Framer
  3.3V supply with 5V tolerant I/O; low powerCMOS
  Available in 128pin TQFP package
  IEEE 1149.1 support


Specifications

Voltage on Any Non-Supply Pin Relative to Ground ..........   1.0V to +5.5V
Supply Voltage ................................................................... -0.3V to +3.63V
Operating Temperature for DS21Q42T................................. .... . 0 to 70
Operating Temperature for DS21Q42TN ...............................40 to +85
Storage Temperature .........................................................55 to +125


Description

The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains fourframers that are configured and read through a common microprocessor compatible parallel port. Eachframer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. Allfour framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.Also the transmit and receive sides of each framer are totally independent. The dual two-frame elasticstores contained in each ofthe four framers can be independently enabled and disabled as required. Thedevice fully meets all of the latest T1 specifications including ANSI T1.4031995, ANSI T1.2311993,AT&T TR 62411 (1290), AT&T TR54016, and ITU G.704 and G.706.