DS90LV049

Features:

·Up to 400 Mbps switching rates
·Flow-through pinout simplifies PCB layout
·50 ps typical driver channel-to-channel skew
·50 ps typical receiver channel-to-channel skew
·3.3 V single power supply design
·TRI-STATE output control
·Internal fail-safe biasing of receiver inputs
·Low power dissipation (70 mW at 3.3 V static)
·High impedance on LVDS outputs on power down
·Conforms to TIA/EIA-644-A LVDS Standard
·Industrial operating temperature range (−40°C to +85°C)
·Available in low profile 16 pin TSSOP package

Pinout






Specifications

Supply Voltage (VDD) −0.3 V to +4 V
LVCMOS Input Voltage (DIN) −0.3 V to (V_DD + 0.3 V)
LVDS Input Voltage (RIN+, RIN-)−0.3 V to +3.9 V
Enable Input Voltage (EN, EN)−0.3 V to (V_DD + 0.3 V)
LVCMOS Output Voltage (DIN) −0.3 V to (V_DD + 0.3 V)
LVDS Output Voltage (DOUT+, DOUT-)−0.3 V to +3.9 V
LVCMOS Output Short Circuit Current (ROUT) 100 mA
LVDS Output Short Circuit Current (DOUT+, DOUT−) 24mA
LVDS Output Short Circuit Current Duration(DOUT+, DOUT−) Continuous
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering (4 sec.) +260°C
Maximum Junction Temperature +150°C
Maximum Package Power Dissipation @ +25°C
MTC Package 866 mW
Derate MTC Package 6.9 mW/°C above +25°C
ESD Rating
(HBM, 1.5 kΩ, 100 pF) 7 kV
(MM, 0 Ω, 200 pF) 250 V

PHY Type	Driver/Receiver Pair
Family	LVDS
Channels	4 Channels
Max Data Rate	400 Mbps
Input Compatibility	LVTTL/LVDS
Output Compatibility	LVTTL/LVDS
Power Consumption_	70 mW
Special Features	Dual Pair
SupplyVoltage	3.3 Volt
JTAG1149.1	No
Temperature Min	-40 deg C
Temperature Max	85 deg C
Automotive Selection Guide	No
Function	Driver/Receiver
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Description

The DS90LV049 is a dual CMOS flow-through differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV049 drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. On the other hand, the receivers accept LVDS signals and translate them to 3 V CMOS signals. The LVDS input buffers have internal failsafe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049 supports a TRI-STATE function for a low idle power state when the device is not in use.

The DS90LV049 EN and EN inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.