DS92LV040A

Features:

·Bus LVDS Signaling
·Propagation delay: Driver 2.3ns max, Receiver 3.2ns max
·Low power CMOS design
·100% Transition time 1ns driver typical, 1.3ns receiver typical
·High Signaling Rate Capability (above 155 Mbps)
·0.1V to 2.3V Common Mode Range for VID = 200mV
·70 mV Receiver Sensitivity
·Supports open and terminated failsafe on port pins
·3.3V operation
·Glitch free power up/down (Driver & Receiver disabled)
·Light Bus Loading (5 pF typical) per Bus LVDS load
·Designed for Double Termination Applications
·Balanced Output Impedance
·Product offered in 44 pin LLP (Leadless Leadframe
·Package) package
·High impedance Bus pins on power off (V_CC = 0V)


Pinout




Specifications

Supply Voltage (VCC)                                                   4.0V
Enable Input Voltage (DE, RE)           −0.3V to (V_CC +0.3V)
Driver Input Voltage (DIN)                 −0.3V to (V_CC +0.3V)
Receiver Output Voltage (ROUT)        −0.3V to (V_CC +0.3V)
Bus Pin Voltage (DO/RI±)                           −0.3V to +3.9V
ESD (Note 4) (HBM 1.5 kΩ, 100 pF)                             >4kV
Machine Model                                                          >250V
Maximum Package Power Dissipation at                   25°C
LLP(Note 3)                                                               4.8 W
Derate LLP Package                                       38.8mW/°C
ja (Note 3)                                                       25.8°C/W
jc                                                                     25.5°C/W
Storage Temperature Range               −65°C to +150°C
Lead Temperature (Soldering, 4 sec.)                    260°C

Description

The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single 3.3V power supply and includes four differential line drivers and four receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The DS92LV040A driver translates 3V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation while consuming minimal power and reducing EMI. In addition, the differential signaling provides common mode noise rejection greater than ±1V. The receiver threshold is less than +0/−70 mV. The receiver translates the differential Bus LVDS to standard (LVTTL/LVCMOS) levels. (See Applications Information Section for more details.)