DS92LV1260

Features:

Deserializes one to six BusLVDS input serial data streams with embedded clocks
Seven selectable serial inputs to support n+1 redundancy of deserialized streams
Seventh channel has single pin monitor output that reflects input from seventh channel input
Parallel clock rate up to 40MHz
On chip filtering for PLL
Absolute maximum worst case power dissipation = 1.9W at 3.6V
High impedance inputs upon power off (Vcc = 0V)
Single power supply at +3.3V
196-pin LBGA package (Low-profile Ball Grid Array) package
Industrial temperature range operation: −40˚C to +85˚C




Specifications

Function	Deserializer
Total Throughput	2400 Mbps
Payload/Channel	400 Mbps
Clock Min	20 MHz
Clock Max	40 MHz
Input Compatibility	LVDS/BLVDS
Output Compatibility	LVTTL
Start/Stop Bit	Yes
SupplyVoltage	3.3 Volt
Temperature Min	-40 deg C
Temperature Max	85 deg C
Compression Ratio	10:1
Number Receivers	6
Communications	Yes
Sensing & Imaging	Yes
Parallel Bus Width	10 bits
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If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vcc) -0.3 to 4V
Bus LVDS Input Voltage(Rin +/-)
-0.3V to 3.9V
Maximum Package
Power Dissipation@ 3.7W
Package Thermal Resistance
JA 196 LBGA: 34˚C/W
JC 196 LBGA: 8˚C/W
Storage Temp. Range-65˚C to +150˚C
Junction Termperature +150˚C
Lead Temperature(Soldering 10 Sec) +225˚C
ESD Rating:
Human Body Model >3KV
Machine Model >750V
Reliability Information
Transistor Count 35,682

Description

The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the National Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input.

Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lock-detect signaling.

The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.

Application Notes

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Title	Size in Kbytes	Date
AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask	339 Kbytes	2-May-04	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the National Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input.

Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lock detect signaling.

The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.