DSP56824

Features: • Efficient 16-bit DSP56800 family DSP engine• As many as 35 Million Instructions Per Second (MIPS) at 70 MHz• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)• Two 36-bit accumulators including extension bits• 16-bit bidirectional barrel shift...

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SeekIC No. : 004329631 Detail

DSP56824: Features: • Efficient 16-bit DSP56800 family DSP engine• As many as 35 Million Instructions Per Second (MIPS) at 70 MHz• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (M...

floor Price/Ceiling Price

Part Number:
DSP56824
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

• Efficient 16-bit DSP56800 family DSP engine
• As many as 35 Million Instructions Per Second (MIPS) at 70 MHz
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with unlimited depth



Pinout

  Connection Diagram


Specifications

Rating Symbol Value Unit
Supply voltage VDD 0.3 to 4.0 V
All other input voltages VIN (GND 0.3) to (VDD + 0.3) V
Current drain per pin excluding VDD and GND I 10 mA
Storage temperature range TSTG 55 to 150 °C



Description

The DSP56824 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). This general purpose DSP combines processing power with configuration flexibility, making it an excellent cost-effective solution for signal processing and control functions. Because of its low cost, configuration flexibility, and compact program code, the DSP56824 is well-suited for cost-sensitive applications, such as digital wireless messaging, digital answering machines/feature phones, modems, and digital cameras.

The DSP56800 core consists of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MPU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers. The DSP56824 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The rich set of programmable peripherals and ports provides support for interfacing multiple external devices, such as codecs, microprocessors, or other DSPs. The DSP56824 also provides two external dedicated interrupt lines and sixteen to thirty-two General Purpose Input/Output (GPIO) lines, depending on peripheral configuration (see Figure 1).


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