Features: • Efficient 16-bit engine with dual Harvard architecture• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)• Four (4) 36-bit accumulators including extension bits• 16-bit bidir...
DSP56858: Features: • Efficient 16-bit engine with dual Harvard architecture• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency• Single-cycle 16 × 16-bit parallel Multiplie...
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Characteristic | Symbol | Min | Max | Unit |
Supply voltage, core | VDD 1 | VSS 0.3 | VSS + 2.0 | V |
Supply voltage, IO Supply voltage, analog |
VDDIO 2 VDDIO 2 |
VSSIO 0.3 VSSA 0.3 |
VSSIO + 4.0 VDDA + 4.0 |
V |
Digital input voltages Analog input voltages (XTAL, EXTAL) |
VIN VINA |
VSSIO 0.3 VSSA 0.3 |
VSSIO + 5.5 VDDA + 0.3 |
V |
Current drain per pin excluding VDD, GND | I | - | 8 | mA |
Junction temperature | TJ | -40 | 120 | |
Storage temperature range | TSTG | -55 | 150 |
The 56858 is a member of the 56800E core-based family of controllers. This device combines the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals on a single chip to create an extremely cost-effective solution. The low cost, flexibility, and compact program code make this device well-suited for many applications. The 56858 includes peripherals that are especially useful for teledatacom devices; Internet appliances; portable devices; TAD; voice recognition; hands-free devices; and general purpose applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications.
The 56858 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56858 also provides two external dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56858 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot RAM. It also supports program execution from external memory.
This 56858 controller also provides a full set of standard programmable peripherals that include an 8-bit Parallel Host Interface, two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer. The Host Interface, Quad Timer, SSI, SPI, SCI I/O and four chip selects can be used as General Purpose Input/Outputs when its primary function is not required.