EM44CM1688LBA

The EM44CM1688LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 8Mbits x 8 banks by 16 bits.This synchronous device EM44CM1688LBA achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1,(3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.

Features of the EM44CM1688LBA are:(1)JEDEC standard VDD/VDDQ=1.8V ±0.1V; (2)all inputs and outputs are compatible with SSTL_18 interface; (3)fully differential clock inputs (CK,/CK) operation; (4)8 banks; (5)posted CAS; (6)burst length: 4 and 8; (7)programmable CAS latency (CL): 3, 4 and 5; (8)programmable additive latency (AL):0, 1, 2, 3 and 4; (9)write latency (WL) =read latency (RL) -1; (10)read latency (RL) = programmable additive latency (AL) + CAS latency (CL); (11)bi-directional differential data strobe (DQS); (12)data inputs on DQS centers when write; (13)Data outputs on DQS, /DQS edges when read; (14)on chip DLL align DQ, DQS and /DQS transition with CK transition; (15)DM mask write data-in at the both rising and falling edges of the data strobe.

The absolute maximum ratings of the EM44CM1688LBA can be summarized as:(1)storage temperature range:-55 to 100;(2)operating temperature range:0 to 85;(3)input,output voltage range:-0.5 to 2.3V;(4)power supply voltage:-0.5 to 2.3V;(5)power dissipation:1W;(6)short circuit current:50mA.Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.The ODT function can be used for all active and standby modes. ODT is turned off and not supported in self-refresh mode.