EM638325TS-6

The EM638325TS-6 is designed as a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512Kx32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512Kx32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

EM638325TS-6 has thirteen features. (1)Clock rate: 200/183/166/143/125/100 MHz. (2)Fully synchronous operation. (3)Internal pipelined architecture. (4)Four internal banks (512Kx32bitx4bank). (5)Programmable mode. (6)Burst stop function. (7)Individual byte controlled by DQM0-3. (8)Auto refresh and self refresh. (9)4096 refresh cycles/64ms. (10)Single +3.3V±0.3V power supply. (11)Interface: LVTTL. (12)Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm pin pitch. (13)Lead free package available. Those are all the main features.

Some absolute maximum ratings of EM638325TS-6 have been concluded into several points as follow. (1)Its input output voltage would be from -1V to 4.6V. (2)Its power supply voltage would be from -1V to 4.6V. (3)Its operating temperature range would be from 0°C to 70°C. (4)Its storage temperature range would be from -55°C to 150°C. (5)Its soldering temperature 10s would be 260°C. (6)Its power dissipation would be 1W. (7)Its short circuit output current would be 50mA. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device.

Also some electrical characteristics of EM638325TS-6 are concluded as follow. (1)Its input leakage current would be min -1.5uA and max 1.5uA. (2)Its LVTTL output high voltage would be min 2.4V. (3)Its LVTTL output low level voltage would be max 0.4V. (4)Its self refresh current would be 2mA. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!