EP1C12

Features:

· 2,910 to 20,060 LEs, see Table 1
· Up to 294,912 RAM bits (36,864 bytes)
· Supports configuration through low-cost serial configuration device
· Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
· Support for 66-MHz, 32-bit PCI standard
· Low speed (311 Mbps) LVDS I/O support
· Up to two PLLs per device provide clock multiplication and phase shifting
· Up to eight global clock lines with six clock resources available per logic array block (LAB) row
· Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
· Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPP^SM) megafunctions


Specifications

Symbol	Parameter	Conditions	Minimum	Maximum	Unit
VCCINT	Supply voltage	With respect to ground (3)	0.5	2.4	V
VCCIO			0.5	4.6	V
VI	DC input voltage		0.5	4.6	V
IOUT	DC output current, per pin		25	25	mA
TSTG	Storage temperature	No bias	65	150
TAMB	Ambient temperature	Under bias	65	135
TJ	Junction temperature	BGA packages under bias		135

Description

Cyclone devices EP1C12 contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.

The logic array EP1C12 consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions.

LABs EP1C12 are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.

M4K RAM blocks EP1C12 are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 200 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.

Each Cyclone device EP1C12 I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66-MHz, 32-bit PCI standard and the LVDS I/O standard at up to 311 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).

Cyclone devices EP1C12 provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks.

The global clock lines EP1C12 can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.