EP1C3T100C8N

The EP1C3T100C8N is one member of the Cyclone field programmable gate array family that is based on a 1.5-V,0.13-m,all-layer copper SRAM process,with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM.

Features of the EP1C3T100C8N are:(1)2,910 to 20,060 LEs;(2)up to 294,912 RAM bits (36,864 bytes);(3)supports configuration through low-cost serial configuration device;(4)support for LVTTL,LVCMOS,SSTL-2,and SSTL-3 I/O standards;(5)support for 66-MHz,32-bit PCI standard;(6)low speed (311 Mbps) LVDS I/O support;(7)up to two PLLs per device provide clock multiplication and phase shifting;(8)up to eight global clock lines with six clock resources available per logic array block (LAB) row;(9)support for external memory,including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM.

The EP1C3T100C8N contains a two-dimensional row-and column-based architecture to implement custom logic.Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.The logic array consists of LABs,with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions.LABs are grouped into rows and columns across the device.Cyclone devices range between 2,910 to 20,060 LEs.