EP1S20B672C7

The EP1S20B672C7 is based on a 1.5-V, 0.13-m, all-layer copper SRAM process with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. And this device supports various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs), also a future version of the Quartus II software will support differential pin migration.

Features of the EP1S20B672C7 are:(1)10,570 to 79,040 LEs; (2)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (3)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters; (4)Support for numerous single-ended and differential I/O standards; (5)High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps); (6)Differential on-chip termination support for LVDS; (7)Support for remote configuration updates; (8)Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices; (9)Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices; (10)Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices.

The absolute maximum ratings of the EP1S20B672C7 can be summarized as:(1)Supply voltage: -0.5 to 2.4 V;(2)DC input voltage: -0.5 to 4.6 V;(3)DC output current, per pin: -25 to 40 mA;(4)Storage temperature: -65 to 150 °C;(5)Junction temperature: 135 °C. If you want to know more information about the EP1S20B672C7, please download the datasheet in www.seekic.com or www.chinaicmart.com .