EP2A25F672C9

The EP2A25F672C9 is a sub package of the EP2A25. The following is some information about the EP2A25. It is a member of APEX II programmable logic device family. It has 2,750,000 maximum gates, 900,000 typical gates, 24,320 LEs, 152 RAM ESBs, 622,592 maximum RAM bits, 36 true-LVDS channels, 56 flexible-LVDSTM channels, 4 true-LVDS PLLs, 8 general-purpose PLL outputs and 612 maximum user I/O pins.

There are some features as follows: (1) programmable logic device (PLD) manufactured using a 0.15-m alllayer copper-metal fabrication process (up to eight layers of metal): high-performance, low-power copper interconnect, fast parallel byte-wide synchronous device configuration and look-up table (LUT) logic available for register-intensive functions; (2) high-density architecture; (3) low-power operation design: 1.5-V supply voltage, copper interconnect reduces power consumption, multiVoltTM I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces, ESBs offer programmable power-saving mode.

What comes next is about the absolute maximum ratings. (1): VCCINT (supply voltage with respect to ground) is from -0.5 to 2.4 V; (2): VCCIO (supply voltage with respect to ground) is from -0.5 to 4.6 V; (3): VI (DC input voltage) is from -0.5 to 4.6 V; (4): IOUT (DC output current per pin) is from -25 to 25 mA; (5): storage temperature (no bias) is from -65 to +150; (6): ambient temperature (under bias) is from -65 to +135; (7): junction temperature (under bias) is 135 for BGA packages under bias.