MFG:FAIRC Package Cooled:TO-251(IPAK) D/C:09+
MFG: FAIRC
Package Cooled: TO-251(IPAK)
D/C: 09+
Description: These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprie...
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on complimentary half bridge.
|
Symbol |
Parameter |
FQD3P50 / FQU3P50 |
Units | ||
|
VDSS |
Drain-Source Voltage |
-500 |
V | ||
|
ID |
Drain Current |
- Continuous (TC = 100°C) |
-2.1 |
A | |
|
|
- Continuous (TC = 25°C) |
-1.33 |
A | ||
|
IDM |
Drain Current Pulsed (Note 1) |
-8.4 |
A | ||
|
VGSS |
Gate-Source Voltage |
± 30 |
V | ||
|
EAS |
Single Pulsed Avalanche Energy (Note 2) |
250 |
mJ | ||
|
IAR |
Avalanche Current (Note 1) |
-2.1 |
A | ||
|
EAR |
Repetitive Avalanche Energy (Note 1) |
5.0 |
mJ | ||
|
d v/dt |
Peak Diode Recovery dv/dt (Note 3) |
-4.5 |
V/ns | ||
|
PD TJ, TSTG |
Power Dissipation (TA = 25°C) |
2.5 |
W | ||
|
Power Dissipation (TC = 25°C) |
30 |
W/°C | |||
|
0.24 | |||||
|
Operating and |
-55 to +150 |
°C | |||
|
TL |
Maximum lead temperature for soldering purposes,1/8" from case for 5 seconds |
300 |
°C | ||
FQU3P50
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