GAL18V10

Supply voltage V_CC ........................................ -0.5 to +7V
Input voltage applied ........................... -2.5 to V_CC +1.0V
Off-state output voltage applied .......... -2.5 to V_CC +1.0V
Storage Temperature .................................... -65 to 150
Ambient Temperature with
Power Applied ............................................... -55 to 125

1. Stresses above those listed under the "Absolute Maximum Ratings"
    may cause permanent damage to the device.  These are stress only
    ratings and functional operation of the device at these or at any
    other conditions above those indicated in the operational sections of 
    this specification is not implied (while programming, follow the
    programming specifications).

The GAL18V10, at 7.5 ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Eras- able (E²) floating gate technology to provide a very flexible 20-pin PLD.  CMOS circuitry allows the GAL18V10  to consume much less power when compared to its bipolar counterparts.  The E² technol- ogy offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

By building on the popular 22V10 architecture, the GAL18V10 eliminates the learning curve usually associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.  The GAL18V10 OLMC is fully com- patible with the OLMC in standard bipolar and CMOS 22V10 de- vices.

Unique test circuitry and reprogrammable cells of GAL18V10 allow complete AC, DC, and functional testing during manufacture.  As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products.  In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.