GC1012B

Notes:
1. Below 1 KHz the clock loss detect circuit will power down the chip. If the clock loss detect circuit is disabled (bit 5, address 7) and the clock is stopped, the chip may draw up to one Amp of power supply current for approximately 10 seconds. After 10 seconds the current will go down to below 50 mAmps.

Fabricated in high speed CMOS technology, the GC1012B chip is an all digital tuner which can
downconvert and band limit signals from wide band digitized sources. At full rate operation (100 MHz input
rate), the input bandwidth of GC1012B can be up to 50 MHz wide. Any signal within the input bandwidth can be
down-converted to zero frequency, low pass filtered, and output at a reduced sample rate. The chip's output
can be formatted as either a complex data stream, or as a real data stream. The complex samples are
output at rates equal to FO=FCK/D, where FO is the output rate, D is 1, 2, 4, 8, 16, 32 or 64 and FCK is the
input sample (clock) rate. The real output rates are FO=2FCK/D for D equal to 2, 4, 8, 16, 32, or 64.
The signal is low pass filtered to remove out of band energy before the sample rate is decreased. The filter's out of band rejection is over 75 dB and its passband ripple is less than 0.2 dB peak to peak. The passband of the output filter covers 80% of the output bandwidth.

The 28 bit accumulator in the chip's digital oscillator circuit of GC1012B provides a tuning accuracy equal to the input clock rate divided by 228. The tuning resolution at a clock rate of 50 MHz is less than 0.2 Hz giving a tuning accuracy of +/- 0.1 Hz. The phase noise in the oscillator is low enough to provide a spur free dynamic
range of over 75 dB.

The chip's output circuit allows the user to select a real or complex data output format, to select spectral inversion, or to offset the output spectrum by half of the output sample rate. The output's signal gain can be adjusted in 0.03 dB steps. The word size of the output samples are either 10, 12, 14, or 16 bits.
On chip diagnostic circuits are provided to simplify system debug and maintenance.

The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 4 bit address port, read and write strobes, and a control select strobe.

I and Q output registers can be read from the control port to allow an external processor to monitor or process the chip's output samples. These registers are valuable for monitoring the chip's output power in order to set and adjust gain levels.