Purchase GDC21D401B, In-stock GDC21D401B From SeekIC.
MFG:HY D/C:08+
Part Number: GDC21D401B
MFG: HY
D/C: 08+
Description: The Video Decoder(VD) decodes videoelementary stream of MPEG-2(ISO/ICE 13818-2)MP@HL. It support...
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GDC21D401B
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DataSheet
General Description
GDC21D401B General Description
The Video Decoder(VD) decodes video elementary stream of MPEG-2(ISO/ICE 13818-2)MP@HL. It supports the ATSC digital TV video standard, and can be used for the video part of the ATSC digital TV with the Transport Decoder and the VDP(Video Display Processor). Picture decoding timing can be controlled internally for A/V lip synchronization, and externally for Video Trick Mode by host microprocessor via I2C bus. The Video Decoder can extract video user data including caption from video elementary stream, and host microprocessor can read the video user data from the Video Decoder(VD) via I2C. It uses four 16x1M SDRAMs and can support up to 81 MHz memory clock speed.
GDC21D401B Maximum Ratings
|
SYMBOL |
PARAMETERS |
VALUES |
UNIT |
|
VDD |
Power Supply Voltage |
-0.33 to 5.5 |
V |
|
VI |
Digital Input Voltage |
-0.33 to VDD + 0.5 |
V |
|
Vo |
Digital Output Voltage |
-0.33 to VDD + 0.5 |
V |
|
Tstg |
Storage Temperature |
-55 to 125 |
|
|
Pd |
Power Dissipation |
4.6 |
W |
*Note :Absolute Maximum Ratings mean that the safety of the device cannot be guaranteed beyond these values, and this doesn't imply that the device should be operated within these limits.
GDC21D401B Features
· Supports MPEG-2 (ISO/ICE 13818-2) MP@HL
· Supports all video input formats of ATSC digital TV standard
· Supports picture decoding capability up to 1920x1088 30 Frame/Sec
· Supports all kinds of motion compensation methods of MPEG-2
· Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
· Supports DTS synchronization
· Supports VBV delay mode and low delay mode decoding
· Supports film mode decoding (3:2 Pull down)
· Supports high level commands for trick mode
· Supports 8(w)x64(d) internal user data FIFO
· Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
· External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
· Host processor interface: I2C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
· Supports all video input formats of ATSC digital TV standard
· Supports picture decoding capability up to 1920x1088 30 Frame/Sec
· Supports all kinds of motion compensation methods of MPEG-2
· Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
· Supports DTS synchronization
· Supports VBV delay mode and low delay mode decoding
· Supports film mode decoding (3:2 Pull down)
· Supports high level commands for trick mode
· Supports 8(w)x64(d) internal user data FIFO
· Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
· External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
· Host processor interface: I2C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
GDC21D401B Connection Diagram
GDC21D401B
PDF/DataSheet Download
- Datasheet: GDC21D401B
- File Size: 710801 KB
- Manufacturer: HYNIX [Hynix Semiconductor]
- Click here to Download
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