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GDC21D601
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MFG:LGS Package Cooled:QFP208

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Part Number: GDC21D601

MFG: LGS

Package Cooled: QFP208

Description: The GDC21D601 is the HME's 32bit high performance microcontroller unit (MCU). The GDC21D601 contains A...

GDC21D601 General Description

The GDC21D601 is the HME's 32bit high performance microcontroller unit (MCU). The GDC21D601 contains ARM720T, which is a general-purpose 32bit microprocessor, and extensive peripherals: 6 channel 16bit Timer, Watch Dog Timer, 2 channel UART, 2 channel SSPI, 3 channel I2C, Programmable Priority Interrupt Controller, 10 port PIO, 2 channel DMA Controller, External Memory Controller and BUS Controller including chip select logic.

ARM720T is a 32bit Microprocessor with the CPU of the ARM7TDMI, 8KB Cache, enlarged write buffer and Memory Management Unit (MMU). The ARM720T is fully software compatible with the ARM processor family.

GDC21D601 Features

· ARM720T Core
   - This is an ARM7TDMI CPU core with
  8KB cache
  enlarged write buffer
MMU(Memory Management Unit)
  On-chip ICEbreaker debug support
  32-bit x 8 hardware multiplier
  Thumb decompressor
  High-performance 32-bit RISC architecture
  High-density 16-bit insturction set
  Enhanced ARM software toolkit
THUMB code is able to provide up to 65% of
the code size of ARM, and 160% of the
performance of an equivalent ARM processor
connected to a 16-bit memory system.
The MMU supports 4G bytes Virtual address.
The allocation of virtual addresses with
different task ID improves performance in task
switching operations with the cache enabled.
· DMA Controller
- Two Channels with identical function
- Four Gigabytes of address space
- 256 Kbytes transfers to the maximum
- Data Transfer unit : Byte, Half-word, Word
- Two kinds of Bus mode
  Burst mode
Exception mode(Cycle steal)
- Two kinds of address mode
  Single address mode
  Dual address mode
- Two types of Transfer request source
  External I/O request
  Auto-request
- Two kind of fixed priority for channels
- Interrupted when the data transfers are complete
· DRAM Controller
- DRAM access
- Support Word, Half-word, and Byte transaction
- CBR refresh in normal operation and self-refresh in power-down mode
- Support programmable refresh rate
- Support various DRAM access time by setting
   the wait count control register
· Static Memory Controller
- Chip Select up to 8 (Each Bank is 256 MByte)
- Exchangeable Chip Select Active High/Low (CS6 and CS7 only)
- Little-Endian and Big-Endian Memory Support
- Programmable wait-state (up to 16 wait-state)
- Support External BUS Ready Strobe
- Support various type Bus Control timing
- Support Word, Half-word, and Byte transaction
· On-Chip SRAM
- 8k Bytes(2048x32)
- Asynchronous SRAM
- Can write 8/16/32bits data, and read 32bits data
· MCU Controller
- The Memory Map Structure Control signals
- DRAM Power-Down Request and Powr-Down Ack signal
- Generate the Multi Function Pin control signals
- Device Code : $GDC601
· Power Management Unit
- Power On Reset, WD_OF Reset, and S/W Reset
- Status : RESET, Power Down, RUN_FAST, RUN_SLOW
- Provide separated clock for each modules on chip
- Provide BCLKOUT, WD_OF, Power-Down pins for external devices
· Watch Dog Timer
- Watchdog timer mode & interval timer mode
- Eight counter clock sources
- Generate the Power Down reset or the Watch Dog Overflow
· Interrupt Controller
- Asynchronous interrupt controller
- Six external interrupt
- Twenty internal interrupt
- Level or edge triggered
- Mask for each interrupt source
Request of IRQ, FIQ for each interrupt source

GDC21D601 datasheet

GDC21D601
PDF/DataSheet Download

Datasheet: GDC21D601
File Size: 4770121 KB
Manufacturer: HYNIX [Hynix Semiconductor]
Click here to Download

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