GS815018

Because GS815018/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

GS815018/36A support pipelined reads utilizing a rising-edge-triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.

GS815018/36A are implemented with high performance technology and are packaged in a 119-bump BGA.