GTLP10B320

The GTLP10B320 is a 10-bit Universal bus driver andreceiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL t GTLP signal level translation. High speed backplane oper ation is a direct result of GTLP!s reduced output swi (<1V), reduced input threshold levels and output edge rat control. The edge rate control minimizes bus settling time GTLP is a Fairchild Semiconductor derivative of th Gunning Transistor logic (GTL) JEDEC standard JESD8-3 Fairchild!s GTLP has internal edge-rate control and is pr cess, voltage and temperature (PVT) compensated. It function is similar to BTL and GTL but with different outpu
levels and receiver threshold. GTLP output low level is typ ically less than 0.5V, the output level high is 1.5V and th receiver threshold is 1.0V.