GTLP16612

The GTLP16612 is an 18-bit universal bus transceiverwhich provides TTL to GTLP signal level translation. Thedevice is designed to provide a high speed interfacebetween cards operating at TTL logic levels and a back-plane operating at GTLP logic levels. High speed back-plane operation is a direct result of GTLP's reduced outputswing (<1V), reduced input threshold levels and outputedge rate control which minimizes signal settling times.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsunction is similar to BTL or GTL but with different driveroutput levels and receiver threshold. GTLP output low volt-age is typically less than 0.5V, the output high is 1.5V andhe receiver threshold is 1.0V.