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GTLP16612

Features: Bidirectional interface between GTLP and TTL logiclevels Designed with Edge Rate Control Circuit to reduceoutput noise VREF pin provides external supply reference voltage forreceiver threshold Submicron Core CMOS technology for low powerdissipation Special PVT Compensation circuitry to p...

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GTLP16612: Features: Bidirectional interface between GTLP and TTL logiclevels Designed with Edge Rate Control Circuit to reduceoutput noise VREF pin provides external supply reference voltage forreceiver thres...

GTLP16612 Data Sheet

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Part Number:
GTLP16612
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
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Product Details

Description



Features:

Bidirectional interface between GTLP and TTL logiclevels
Designed with Edge Rate Control Circuit to reduceoutput noise
VREF pin provides external supply reference voltage forreceiver threshold
Submicron Core CMOS technology for low powerdissipation
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supplyvoltage and temperature
5V tolerant inputs and outputs on A-Port
Bus-Hold data inputs on A-Port to eliminate the need for
external pull-up resistors for unused inputs
Power up/down high impedance
TTL compatible Driver and Control inputs
A-Port outputs source/sink −32 mA/+32 mA
Flow-through architecture optimizes PCB layout
Open drain on GTLP to support wired-or connection




Pinout






Specifications

Supply Voltage (VCC, VCCQ) .......................−0.5V to +7.0V
DC Input Voltage (VI) ..................................−0.5V to +7.0V
DC Output Voltage (VO)
Outputs 3-STATE....................................... .. −0.5V to +7.0V
Outputs Active (Note 5) .......................−0.5V to VCC + 0.5V
DC Output Sink Current into
A-Port IOL ..................................................................64 mA
DC Output Source Current from
A-Port IOH ...............................................................−64 mA
DC Output Sink Current
into B-Port in the LOW State,
IOL ............................................................................80 mA
DC Input Diode Current (IIK)
VI< 0V ................................................................... .−50 mA
DC Output Diode Current (IOK)
VO < 0V ....................................................................−50 mA
VO > VCC .................................................................+50 mA
Storage Temperature (TSTG) .....................−65 to +150
ESD Performance................................................... ...>2000V




Description

The GTLP16612 is an 18-bit universal bus transceiverwhich provides TTL to GTLP signal level translation. The GTLP16612 is designed to provide a high speed interfacebetween cards operating at TTL logic levels and a back-plane operating at GTLP logic levels. High speed back-plane operation is a direct result of GTLP's reduced outputswing (<1V), reduced input threshold levels and outputedge rate control which minimizes signal settling times.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP GTLP16612 has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsunction is similar to BTL or GTL but with different driveroutput levels and receiver threshold. GTLP GTLP16612 output low volt-age is typically less than 0.5V, the output high is 1.5V andhe receiver threshold is 1.0V.






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