GTLP16617

The GTLP16617 is a 17-bit registered synchronous busransceiver that provides TTL to GTLP signal level transla-ion. It allows for transparent, latched and clocked modesof data flow and provides a buffered GTLP (CLKOUT)clock output from the TTL CLKAB. The device provides ahigh speed interface between cards operating at TTL logicevels and a backplane operating at GTLP logic levels.High speed backplane operation is a direct result ofGTLP's reduced output swing (<1V), reduced input thresh-old levels and output edge rate control. The edge rate con-rol minimizes bus settling time. GTLP is a FairchildSemiconductor derivative of the Gunning Transceiver logicGTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is pro-cess, voltage, and temperature (PVT) compensated. Itsunction is similar to BTL and GTL but with different outputevels and receiver threshold. GTLP output LOW level isypically less than 0.5V, the output level HIGH is 1.5V andhe receiver threshold is 1.0V.