GTLP6C817

Features: Interface between TTL and GTLP logic levels Edge Rate Control to minimize noise on the GTLP port Power up/down high impedance for live insertion 1:6 fanout clock driver for LVTTL port 1:2 fanout clock driver for GTLP port LVTTL compatible driver and control inputs 5V over voltage toleran...

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SeekIC No. : 004357125 Detail

GTLP6C817: Features: Interface between TTL and GTLP logic levels Edge Rate Control to minimize noise on the GTLP port Power up/down high impedance for live insertion 1:6 fanout clock driver for LVTTL port 1:2 ...

floor Price/Ceiling Price

Part Number:
GTLP6C817
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/30

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Product Details

Description



Features:

 Interface between TTL and GTLP logic levels
Edge Rate Control to minimize noise on the GTLP port
Power up/down high impedance for live insertion
1:6 fanout clock driver for LVTTL port
1:2 fanout clock driver for GTLP port
LVTTL compatible driver and control inputs
5V over voltage tolerance on LVTTL ports
Flow through pinout optimizes PCB layout
Open drain on GTLP to support wired-or connection
Recommended Operating Temperature −40 to +85



Pinout

  Connection Diagram


Specifications

Supply Voltage (VCC) ..................−0.5V to +7.0V
DC Input Voltage (VI) ................. −0.5V to +7.0V
DC Output Voltage (VO)
Outputs 3-STATE ......................  .−0.5V to +7.0V
Outputs Active (Note 2) ..............−0.5V to +7.0V
DC Output Sink Current into
OA-Port IOL............................................ . 24 mA
DC Output Source Current
from OA-Port IOH ...................................−24 mA
DC Output Sink Current into
OB-Port in the LOW State IOL................ . 80 mA
DC Input Diode Current (IIK)
VI< 0V ....................................................−50 mA
DC Output Diode Current (IOK)
VO < 0V ..................................................−50 mA
VO > VCC ...............................................+50 mA
ESD Rating ............................................> 2000V
Storage Temperature (TSTG) .....−65 to +150



Description

The GTLP6C817 is a low drive clock driver that providesTTL to GTLP signal level translation (and vice versa). The GTLP6C817 provides a high speed interface between cardsoperating at TTL logic levels and a backplane operating atGTLP logic levels. High speed backplane operation is adirect result of GTLP's reduced output swing (<1V),reduced input threshold levels and output edge rate con-trol. The edge rate control minimizes bus settling time.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transceiver logic (GTL) JEDECstandard JESD8-3.

Fairchild's GTLP GTLP6C817 has internal edge-rate control and is pro-cess, voltage, and temperature (PVT) compensated. GTLP6C817's function is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP GTLP6C817 output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.


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